UGA-VERIMAG is one of the main European laboratories in embedded systems. It develops theory, methods and tools for safety critical and embedded systems. It has been established in 1993. This lab is affiliated with three academic institutions in Grenoble, including UGA. Design and validation of real-time embedded systems is a central subject of research at VERIMAG, which has competences in verification and validation with focus on security and safety, component-based design, language design, synchronous languages, transaction-level modelling of systems-on-chip, formal modelling of wireless sensor networks, theoretical and algorithmic foundations of hybrid systems, etc. VERIMAG has been and is currently involved in many European and national projects, including projects on aircraft systems and airborne software and correct development of real-time embedded systems. Several results of VERIMAG have been transferred to industry.

The RSD team at VERIMAG/UGA works on modular component framework based on Behaviour-Interaction-Priority (BIP) language. The research topics include structural and compositional verification of programs, component-based design and verification of multi-core and network systems, system property enforcement, controller synthesis and real-time scheduling.

UGA-VERIMAG has participated in the following related activities:

  • MoSATT-CMP – ESA-funded project, 2014-2016, on Model-based Schedulability Analysis Techniques and Tools for Cached and Multicore Processors. It concerns with design tools and design methodology for real-time systems. VERIMAG contributes to the TASTE2BIP toolchain, probabilistic WCET analysis, scheduling for mixed-critical systems, and development of a BIP-based scheduler prototype for LEON4 processor.
  • CERTAINTY — European IST, FP7 project, 2011-2014, with aim of development of design tools and methodologies for mixed-critical multi-core systems. VERIMAG has contributed by BIP modelling and multi-core implementation of a Flight Management System use case from Thales.
  • ASSERT — FP6 project, 2004-2008. The TASTE framework itself originates from this project. The project main goal was to improve the system-and-software development process for critical embedded real-time systems. VERIMAG has contributed to verification techniques for application software and scheduling policies.
  • GOAC — ESA-funded project, 2010-2012 led by GMV. DCS BIP has contributed by verification and code generation techniques, especially in the “DALA robot” case study, which has resulted in new important developments in BIP methodology itself.
  • MARAE — This project, 2008-2010, funded by FNRAEs is an industrial project on robust methods to develop autonomous systems. MARAE was interested in the software architecture of space systems, such as monitoring satellites and autonomous robots. DCS-BIP has contributed on component-based construction and verification of robotic systems.